1. Field of the Invention
The present invention relates to an image input apparatus, image input method, and memory medium and, more particularly, to an image input apparatus and image input method of inputting an image of an object as an electrical signal by using an image sensing device, and a memory medium used to control the apparatus.
2. Description of the Related Art
With the recent progress of digital signal processing technologies and semiconductor technologies, a consumer digital video standard by which motion image signals of a standard television system, e.g., the NTSC or the PAL system, are digital-recorded is proposed. Also, as one application of this standard, video cameras integrating a digital video recording/reproduction apparatus and a digital camera have been commercialized.
By making the best use of characteristic features of digital recording, some video cameras of this type include a still image recording function or comprise a digital I/F for connecting a computer or the like to transfer a photographed image to the computer or the like.
To reproduce a photographed image on the screen of a television monitor, a video camera need only include an image sensing device having pixels the number of which is equivalent to the number of pixels (e.g., 720×480 pixels) defined by the digital video standard. However, to supply an image from a video camera to another apparatus via a digital I/F or recording medium (e.g., a video tape), it is desirable to supply an image having the number of pixels meeting the specifications of the apparatus.
One prior art relevant to the present invention is a video camera including an image sensing device having pixels the number of which is larger than the number of finally necessary pixels. One example is a video camera which compensates for camera shake by reading out some pixels of an image sensing device.
FIG. 18 is a block diagram showing the arrangement of a video camera including a camera shake compensating function. This video camera comprises a CCD 2002, a CCD controller 2004, a clock generator 2006, a control signal generator 2010, an A/D converter 2014, a camera signal generator 2016, a memory 2042, a memory controller 2046, an interpolating unit 2044, and a D/A converter 2040. The CCD controller 2004 controls signal read from the CCD 2002. The clock generator 2006 generates a system clock. The control signal generator 2010 generates various control signals in accordance with the output system clock from the clock generator 2006. The A/D converter 2014 converts an output analog signal from the CCD 2002 into a digital signal. The camera signal generator 2016 generates a video signal from the output signal from the A/D converter 2014. The memory 2042 is used to extract a video signal of a predetermined region from the output video signal of a whole region from the camera signal generator 2016 and enlarge the extracted signal. The memory controller 2046 controls the memory 2042. The interpolating unit 2044 interpolates the output video signal from the memory 2042. The D/A converter 2040 converts the output digital video signal from the interpolating unit 2044 into an analog video signal.
FIG. 19A is a schematic view showing processing in a vide camera including a CCD having pixels the number of which is equivalent to the number of finally required pixels. FIG. 19B is a schematic view showing processing in the video camera shown in FIG. 18.
In the video camera shown in FIG. 19A, the CCD has 768 pixels in the horizontal direction and 485 pixels in the vertical direction. This CCD reads out whole information within one field period in synchronism with a 14.3-MHz (910/63.5 μsec) clock.
In the video camera shown in FIG. 19B, the CCD 2002 has 948 pixels in the horizontal direction and 648 pixels in the vertical direction. Signals corresponding to the hatched portions are discarded. For example, a signal corresponding to the upper hatched portion is read out from the CCD 2002 within a short time period by rapid transfer and discarded. A signal of 485 lines is then read out from the CCD 2002 in synchronism with a 18.0-MHz clock. Subsequently, a signal corresponding to the lower hatched portion is read out from the CCD 2002 within a short time period by rapid transfer and discarded.
By executing the above processing in the horizontal and vertical directions, it is possible to obtain an image formed by cutting a predetermined region (in this example, 768 pixels (horizontal)×485 pixels (vertical)) from an image constructed by all pixels of the CCD 2002. Camera shake compensation is realized by changing the cutting position of an image in accordance with camera shake.
Another prior art relevant to the present invention is a digital camera which displays an image sensed by a CCD by decreasing the number of pixels. FIG. 20 is a block diagram showing the arrangement of a digital camera including a CCD having pixels the number of which is larger than the number of pixels of an image to be displayed on a monitor. The same reference numerals as in the video camera shown in FIG. 18 denote essentially the same components in FIG. 20.
In this digital camera, an image signal of all pixels is read out from a CCD 2002 and supplied to a camera signal generator 2016 via an A/D converter 2014. A first memory 2050 records an output video signal from the camera signal generator 2016. A reducing unit 2052 reduces the video signal of a whole region recorded in the first memory 2050 and records the reduced signal in a second memory 2054. This video signal recorded in the second memory 2054 is read out at a common field frequency and output to a D/A converter 2040 so as to be supplied to a monitor functioning as an electronic finder.